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Analog Technologies, Inc.
TECEV103
TEC CONTROLLER EVALUATION KIT TECEV103
(updated 06/17/04) Our TEC controller modules can be evaluated conveniently by using this evaluation kit TECEV103 which comes with an evaluation board, TECEVB103 and a TEC controller module of TEC-A1 (there is no internal compensation network inside). The main purpose of using the evaluation board is to tune the compensation network on the board for matching the characteristics of users' thermal load. The objectives of the tuning are to minimize the response time of the thermal control loop and the dynamic temperature tracking errors, while keeping the control loop stable. 1. Connection
To A/D, D/A, and/or microprocessor To power supply 5V Imax = 2A For For multimeter oscilloscope probing probing
To TEC To Thermistor
TECN +5V GND TECTEC+ Rth GND
TECN
TECP
LEDC
TECP
LEDA TEC RTH Controller Temp. good Vlim On LED TMPS Ri TMPO CMPIN Rp Cd Rd Ci CMPO Off Power On Off TMPS RTH
S3
TMPO
CDRD VDR 3V Cd TMPGD 4.7uF 3.3uF 2.2uF 1.5uF 0 S1 1uF SDNG Wi 2M GND Wd 500K Wp 2M 330nF 470nF 680nF 820nF
CIRP VDR CLHT Ci 1uF 820nF 680nF 470nF 0 S2 330nF SDNG W1 5K W2 5K W3 20K GND 82nF 100nF 150nF 220nF TMPGD
Figure 1 TEC Controller Evaluation Board TECEV103
550 E. Weddell Dr., #4, Sunnyvale, CA 94089 U. S. A. Tel.: (408) 747-9760, Fax: (408) 747-9770. www.analogtechnologies.com
(c) Copyright 1999 - 2004, Analog Technologies, Inc. All Rights Reserved. Updated: 8/25/04
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Analog Technologies, Inc.
TECEV103
Figure 2 TECEV103 Photo positions (down side). Check the evaluation board Figure 1 shows the layout of the evaluation board and Figure connections, making sure that they are all correctly 2 shows its photo. connected. Turn on the Power side switch and see how the Controller works. These are the procedures for the adjustment. 1. Set up basic connections. Connect a 5V DC power supply and the TEC terminals in the right polarity as indicated onto the board. Connect the thermistor terminals to the board, there is no polarity requirement. Turn the two switches, for Vlim and Power, to the off 2. Tune the compensation network. The purpose for this step is to match the controller compensation network with the thermal load characteristics thus that the response time and temperature tracking error are minimized. Adjust the potentiometer W1 to change
550 E. Weddell Dr., #4, Sunnyvale, CA 94089 U. S. A. Tel.: (408) 747-9760, Fax: (408) 747-9770. www.analogtechnologies.com
(c) Copyright 1999 - 2004, Analog Technologies, Inc. All Rights Reserved. Updated: 8/25/04
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Analog Technologies, Inc.
the set-point temperature TMPS just a small amount, simulating a step function. At the same time, connect an oscilloscope at the VDR test pin (on the right side of the evaluation board), set it to a scrolling mode (0.2 Second/Division or slower) and monitor the waveform of VDR as TMPS is fed by a step function signal. The circuit in the compensation network is shown in Figure 3 below.
Rd Rp
TECEV103
frequency goes down. It determines the cut-off frequency below which the TEC controller will start having a large open loop gain. The higher the open loop gain, the smaller the tracking error will be. d. Cd*Ri determines the corner frequency, 2=1/(Cd*Ri), where the differential component starts picking up (see Figure 4), as the frequency goes up. Cd*Rd determines the corner frequency, 3=1/(Cd*Rd), where the differential component starts getting flat. It determines the cut-off frequency above which the TEC controller will give extra weight or gain in response. Cf*Rp determines the corner frequency, 4=1/(Cf*Rp), where the differential component starts rolling down. Since this frequency is way higher than being needed for controlling the TEC, 4 does not need to be tuned. The capacitor is built into the TEC controller module, not the evaluation board.
e.
Cf Cd TMPO Ri -
Ci
f.
VDR TMPS +
Figure 3 Compensation network The transfer function of the compensation network, defined as H()=VDR()/TMPO(), is shown in figure 4.
H( )
Gd 0.71Gd 1.41Gp Gp 1 2 3 4
To start the tuning, turn off the differential circuit by setting Cd Open. Turn W1 quickly by a small angle, back and forth, approximately 5 seconds per change. Set Ci to 1uF, set Ri to 1M, and increase the ratio of Rp/Ri as much as possible, provided the loop is stable, i.e. there are no oscillations seen in VDR. Then, minimize Ci as much as possible, provided the loop is stable. The next step is to minimize Rd and maximize Cd while maintaining about 10% overshoot found in VDR. Optimum result can be obtained after diligent and patient tuning. The tuning is fun and important. When the TEC controller is used for driving a TEC to stabilize the temperature of a diode laser, there is no need to turn on the laser diode while tuning the TEC controller. To simulate the active thermal load given by the laser diode, setting the set-point temperature lower than the room temperature is enough. For a typical laser head used in EDFA's or laser transmitters (found in DWDM applications, for instance), Ri = 1M, Rp = 1M, Ci = 680nF, Cd = 1.5F, and Rd = 250k. These values may vary, depending on the characteristics of a particular thermal load. To be conservative in stability, use larger Ci and larger Ri; To have quicker response, use smaller Rd and larger Cd. The closer to the TEC the thermistor is mounted, the easier to have the loop stabilized, the shorter the rise time and the settling time of the response will be. 3. After tuning, the values of the capacitors for Cd and Ci can be read off the capacitor selection switches. The values of the resistors, Ri, Rd and Rp, can be measured by an Ohm-meter by connecting to the resistor pins. As seen in the photo of Figure 2, Ri can be read off between TMPO and CMPIN test points; Rd can be read off
Figure 4 Transfer Function of the Compensation Network In principle, these are the impacts of the components to the tuning results: a. Rp/Ri determines the gain for the proportional component of the feedback signal which is from the thermistor, Gp = Rp/Ri, in the control loop, the higher the gain, the smaller the short term error in the target temperature (which is of the cold side of the TEC) compared with the set-point temperature, but the higher the tendency of the loop's instability. Rp/Rd determines the gain for the differential component, Gd = Rp/(Rd//Ri) Rp/Rd, where symbol "//" stands for two resistors in parallel, since Ri >> Rd, Rd//Ri = Rd. The higher the gain, the shorter the rise time of the response, the more the overshoot and/or the undershoot will be. Ci*Rp determines the corner frequency, 1= 1/(Ci*Rp), where the integral component starts picking up, as the
b.
c.
550 E. Weddell Dr., #4, Sunnyvale, CA 94089 U. S. A. Tel.: (408) 747-9760, Fax: (408) 747-9770. www.analogtechnologies.com
(c) Copyright 1999 - 2004, Analog Technologies, Inc. All Rights Reserved. Updated: 8/25/04
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Analog Technologies, Inc.
between CMPIN and CDRD test points; Rp can be read off between CMPIN and CIRP test points. 4. After the compensation network is tuned properly, we can now adjust set-point temperature to see if the TEC controller can drive the target temperature to a certain range and with high stability. Turn the temperature setpoint TMPS potentiometer W1 while monitoring its output voltage at TMPS test point (4th row on either left or right side of the board), watch the LED: when it turns to green, the target temperature is locked to the set-point temperature within 0.1C or less. The relationship between the set-point voltage vs. the set-point temperature is given in the datasheet. After seeing the LED lock into the set-point temperature, VDR should be a constant voltage as shown in the oscilloscope and the voltage between TMPS and TMPO should be very small, less than 10mV. When a standard TEC controller is used, the 10mV represent a 0.07 temperature error. 5. Set output voltage limit. 6. To know more parameters of the TEC controller. a. To know the actual target temperature, use a voltage meter to measure the voltage between the TMPO and the GND pins, the reading result is: target temperature = 15C + (TMPO voltage (V))*6.67C for approximation (see the curve in the TEC controller data sheet). b. To know how hard the TEC is working, measure the voltage VDR by a voltage meter or an ADC, TEC voltage = 2.5V - VDR. When the TEC voltage (from the calculation) is positive, it is in cooling mode; when the TEC voltage is negative, it is in heating mode. Cool/Heat Balance CLHT can be adjusted by W2. TEC maximum voltage can be reduced by reducing W3, make sure Vlim switch is now turned to the on position. c. To try other values of capacitors not provided by the evaluation board for the capacitors in the compensation network, turn the capacitor switches you want to try to the top point, the "0" position, connect the component to the corresponding soldering pads as marked on the evaluation board. d. To shut down the TEC controller, turn the Power switch to the "Off" position, see Figure 2. e. To control the set-point temperature directly by using a DAC, set the set-point temperature POT W1 to the middle point (25C), on which the TMPS is about 1.5V, the half value of the reference voltage, connect TMPS test point to the output of the DAC and use this formula for approximation when the input voltage is between 0V and 3V: set-point temperature (C) = 15C + (TMPO voltage (V))*6.67C. The maximum voltage allowed is Vps (power supply). See the curve in the TEC controller data sheet.
TECEV103
f. To control the TEC voltage directly by using a DAC, connect VDR to the output of the DAC and use this formula: TEC voltage = 2.5V - VDR (V). g. To shut down the TEC controller by using a microprocessor, turn off the Power switch, connect SDN test point (2nd row from the bottom side, on both left and right columes.) to one of its digital outputs. When pulling low, the TEC controller is shut off. When pulling high SDN, the TEC controller is turned on. h. The evaluation schematic is given in Figure 5. Using the TEC controller for more applications not described here, and/or having any questions, please free to contact us.
550 E. Weddell Dr., #4, Sunnyvale, CA 94089 U. S. A. Tel.: (408) 747-9760, Fax: (408) 747-9770. www.analogtechnologies.com
(c) Copyright 1999 - 2004, Analog Technologies, Inc. All Rights Reserved. Updated: 8/25/04
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Analog Technologies, Inc.
TMPO 1 2 1 R I 2 1 S 1 1 2 CD1 330nF 2 1 CD2 470nF 2 1 1 2 3 WD 500K R P 2 WI 2M 3
TECEV103
C PO M Left S ide R Side ight THL1 TEC N 1 TEC THL2 TEC P 1 TEC + THL3 R TH 1 R TH THL4 T PS M 1 TMPS T PO M THL6 VDR 1 VDR THL7 TMPGD 1 T PGD M THL8 1 S DN THL9 GND 1 GND LEDC 1 3V 1 GND 1 GND CHB B ottomSide 1 1 TMPGD 1 TMPGD THR8 1 S DN THR9 GND 1 VDR 1 VDR THR7 TMPGD 1 1 TMPO THR6 VDR 1 TMPS 1 TMPS THR5 TMPO 1 R TH 1 R TH THR4 TMPS 1 TEC P 1 TEC + THR3 R TH 1 TEC N 1 TEC THR2 TEC P 1 THR1 TEC N 1 TT1 TEC N TEC TT2 TEC P TEC + TT3 R TH R TH TT4 TMPS TMPS TT5 TMPO TMPO TT6 VDR VDR TT7 TMPGD TMPGD S DN 1 TT8 S DN S DN TT9 GND GND LEDA S_Pad LEDC S_Pad 1 1 1 1 1 1 1 1 1 S1 PR 1 S _Pad TEC S2 PR S _Pad TEC + S3 PR S _Pad R TH S4 PR S _Pad TMPS S5 PR S _Pad TMPO S6 PR S _Pad VDR S7 PR S _Pad TMPGD S8 PR S _Pad S DN S9 PR S _Pad GND GND 1 R TH 1 TEC P 1 TEC N 1 PGND 1 5V 1 Top S ide S PT1 L_Pad 5V S PT2 L_Pad 0V S PT3 L_Pad TEC S PT4 L_Pad TEC + S PT5 S _Pad R TH-1 S PT6 S _Pad R TH-2(GND)
Ri
C PIN WP 2M M 3 1
Rp Ci 82nF
1 1 2 3 4 S 2 S T9P
2
S PL1 TEC N 1 S _Pad TEC S PL2 TEC P 1 S _Pad TEC + S PL3 R TH 1 S _Pad R TH S PL4 TMPS 1 S _Pad TMPS S PL5 TMPO 1 S _Pad TMPO S PL6 0 VDR 1 S _Pad VDR S PL7 TMPGD 1 S _Pad TMPGD S PL8 S DN 1 S _Pad S DN S PL9 GND 1 S _Pad GND LEDA S DN
C I1 2
C 100nF I2 2 1 C 150nF I3 2 1 C 220nF I4 2 1
CD3 680nF 32 1 CD4 820nF 42 1 CD5 1uF 52 1 0 6 7 S T9P 8 CD6 1.5uF 1 2 CD7 2.2uF 1 2 CD8 3.3uF 1 2 1
R D
2
C 330nF I5 2 1 C I6 2
5
470nF 1 6 7 8 9
C I7 680nF 2 1 C I8 820nF 1 2
S DN
CD9 4.7uF 92 1
Cd
Rd
C I9 1uF 1 2
10 2
C D 1
C I 1
10 2
1
1
1
1
1
TM H1 TMPO U1 TMPGD 3V TMPS 1 2 3 4 VDR C PO M C PIN M T PO M 5 6 7 8 TEMPGD 3V TEMPSP GND TEC R CT VTEC C IN M TEM P TECA1 VPS GNDP GNDP TECNEG TEC POS R TH GND S DNG
THM2 CDRD
THM3 C PIN M
THM4 CP IR
THM5 C PO M
1 THM6 LEDA
TM H7 LEDC
TM H8 3V
THM9 C LHT
S1 PM LEDA 16 15 14 13 12 11 10 9 S DN 5V PGND T PS M TEC N TEC P R TH 2 2 1 3V 3 W1 W2 5K 5K 1 1 R 1 100 1 R 2 10K MB M T6428 2 2 5V 3 CHB W3 20K 2 1 3 5V 2 1 S 3 3 4 N1206-4 S DN VDR 3 LEDC LED1 1 2 1 S L-LX2832SUGC M 4 1 2R 100K 1 TMPGD LEDA R 3 1K 2 5V
S2 PM LEDC
2
Q1
TECEV-103
Figure 5 Evaluation Board Schematic
550 E. Weddell Dr., #4, Sunnyvale, CA 94089 U. S. A. Tel.: (408) 747-9760, Fax: (408) 747-9770. www.analogtechnologies.com
(c) Copyright 1999 - 2004, Analog Technologies, Inc. All Rights Reserved. Updated: 8/25/04
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